Job description
Role: DFT Engineer
Location: San Jose, CA (Onsite)
Job Type: Full time Role
Job Description:
4-8 years with Low power design experience
SCAN ATPG, Debug, Constratints, STUCK, Transition, Bridge. DFT, TCL, PERL,
JOB DETAIL
a. Experience with Scan, Debug and resolve implementation issues
b. Experience with Timing Constraint
c. ATPG (stuck, transition delay, bridge) with Synopsys tools
d. Ability to debug ATPG simulation failures is a plus
e. DFT insertion using DFT Compiler - Good TCL and PERL scripting skills
Thanks & Regards
Manvendra Yadav
Plaxonic Technologies Inc
manvendra@plaxonic.com
727-241-5655
linkedin.com/in/manvendra-yadav-65570b117
Job Type: Full-time
Salary: $200,000.00 - $210,000.00 per year
Schedule:
- 8 hour shift
Experience:
- Design for testing: 4 years (Required)
- Stuck: 3 years (Required)
- Low Power design: 4 years (Required)
Work Location: On the road
Speak with the employer
+91 727-241-5655
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