Job description
NantWorks (the “Company”) is the parent company of various private and public entities that are changing how we work, live and play. We focus on three main categories: life sciences; energy & renewables; and media & technology. We invest in strategies that improve our core capabilities and in brand new industries, poised to change mankind for the better. By capturing tomorrow’s opportunities through scientific processes and entrepreneurial philosophies, we are at the forefront of emerging high-growth technologies across a wide range of industries.
The Company is a mandatory vaccination employer for COVID-19 and its variants. The Company requires that its employees be fully vaccinated as of their start date. If you require a medical or religious accommodation we will engage in the interactive process with you. Proof of vaccination will be required prior to start. If we make you an offer and you are not yet vaccinated, we will accommodate a delay in start date. The Company may also mandate that its employees receive vaccine boosters, and all accommodation laws will be followed.
Tensorcom, a member of the NantWorks™ family of companies, is a privately-held fabless semiconductor company headquartered in Carlsbad, California. The company has pioneered cutting edge technology for high-speed millimeter wave wireless communication and offers ultra-low power products supporting the 802.11ad WiGig standard.
Tensorcom has assembled a world class team of experts with extensive experience in communication system design, 60 GHz CMOS RFIC design and ultra-low power baseband and SoC implementation.
Position Summary:
We are a pioneer in cutting edge technology for high speed millimeter wave wireless communication and offers ultra-low power products supporting 802.11ad WiGig standards.
In this role, the FPGA Design Engineer will have an opportunity to work on complex ASIC designs for our 60GHz 802.11ad SoC, including mixed-signal Beam forming RFIC. The candidate will work on many phases of ASIC development process ranging from architecture, design to tape-out, and chip bring-up.
Responsibilities:
- RTL design of digital circuits using Verilog/Systemverilog/VHDL
- Testbench and test case development
- ASIC emulation on FPGA boards
- Consult with software and ASIC design team to resolve issues during the development process
Education and Experience:
- Bachelor's degree in Electronic, VLSI Engineering or related field with 0-2 years experience within the following areas:
- Design flow
- Xilinx Vivado, Synplify Synthesis, Xcelium simulation
- Design language: VHDL and/or Verilog/Systemverilog
- Processor subsystem
- Understanding of processor architecture, memory, bus fabric, and interface IPs
- Hardware/Software interfacing
- Verification
- Testbench and test cases development
- ASIC emulation on FPGA development platforms
- Lab skills
- FPGA board bring-up
- Comfortable with laboratory testing and measurement equipment
- Oscilloscope, logic analyzer, power supplies
- New graduates or soon to be graduated are welcome to apply
- All hires are based upon completion and passage of a background check
The specific rate will depend on the successful candidate’s qualifications, prior experience as well as geographic location.
$76,000.00 (entry-level qualifications) to $84,000.00 (highly experienced)
This is the pay range the Company reasonably expects to pay for this position at the time of this posting. Compensation will be determined based on the skills, qualifications, and experience of the applicant along with the requirements of the position.
We offer competitive benefits, including health, dental and vision insurance, 401k, short-term and long-term disability insurance, life insurance, 11 designated holidays, Paid Time-Off program, and Employee Assistance Program.
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